1. Field of the Invention
The present invention relates to a method for forming copper interconnections in a semiconductor component using an electroless plating system, and more particularly to such a method, in which a metal seed for growing copper interconnections is subjected to a selective pretreating process, so as to grow copper only in corresponding interconnection regions.
2. Description of the Prior Art
Up to the present, aluminum (Al) and tungsten (W) have been used for metal interconnection process in semiconductor components, but copper (Cu) having lower resistance and better metal properties has recently been used as a substitute and many studies on copper interconnection processes are now in progress. A copper deposition process by use of an electrolytic plating system is already employed in some semiconductor components. The copper deposition method includes a chemical vapor deposition (CVD) system, a sputtering system, an electrolytic plating system and so forth. The conventional vacuum deposition systems, however, have many difficulties in developing copper metal-organic compounds and the sputtering system has problems including its incapability to form a uniform copper film.
A description will be given here for a conventional copper interconnection process in a semiconductor component.
FIGS. 1A and 1B are schematic sectional views showing the conventional process of forming copper interconnections. Referring to FIGS. 1A and 1B, interconnections with various shapes are fabricated by growing an interlayer dielectric (ILD) film 2 on a silicon wafer 1 and performing a photo process and an etching process to form via holes and trenches. The interlayer dielectric film 2 is formed using a silicon oxides (SiO2) film or a fluorosilicate glass (FGS) film, i.e., a silicon oxyfluoride (SiOF) film. After a cleaning process, a metal diffusion barrier (Ta, Ti, TaN, TiN) layer 3 with a predetermined thickness is then deposited on the interlayer dielectric film 2 by a sputtering method. At this time, if the via holes have high aspect ratios, a collimated system capable of improving step coverage is used in the sputtering deposition of the layer to be bonded.
After a thin copper seed layer 4 is deposited on the metal diffusion barrier layer 3 by the sputtering method, a copper interconnection layer 5a is filled in the via holes and the trenches and is further deposited over the entire regions to be processed. At this time, the copper interconnection layer 5a may be formed using an electroless plating method, an electrolytic plating method, a sputtering method or a CVD method, among which the electrolytic plating method or the CVD method shows an excellent via hole-fling characteristic. In the case of using the electrolytic plating method, the copper seed layer must be deposited in advance with a thickness of 100 to 1000xc3x85.
Subsequently, the copper interconnection layer 5a, the metal diffusion barrier layer 3 and the copper seed layer 4 over the interlayer dielectric film 2 are removed using a chemical mechanical planarization (CMP) method or a combination of an electrolytic polishing method and the chemical mechanical planarization method in order to proceed with semiconductor component processes on the deposited copper interconnection layer. In this way, the copper 5b comes to be only in the patterned interconnections.
A process for preventing copper atoms within the copper interconnection layer 5b from diffusing into the interlayer dielectric film 2 is also performed by full deposition of a capping layer (not shown), using a silicon nitride film or the like, over the entire structure including the interlayer dielectric film 2 and the copper interconnection layer 5b. 
Meanwhile, many studies have been conducted in an effort to achieve spontaneous surface activation in the electroless plating system. In general, these studies were conducted with the intention of producing a seed solution using palladium and depositing palladium particles on the wafer in various ways. Recently, a deposition system has been used, in which the wafer is coated with a palladium seed solution using a spin coating method, palladium particles are deposited in desired regions by exposing the coated wafer to a ultraviolet radiation so as to maintain palladium bonded to exposed portions of the wafer and remove palladium in non-exposed portions of the wafer using a photo process and a cleaning process and then copper is selectively deposited by performing electroless plating. This deposition system involving the photo process, however, is problematic because it is very difficult to produce an efficient palladium seed solution for the photo process.
With regard to conventional electrolytic plating being used for the metal interconnection process, there have been various difficulties including deterioration of electrical properties of the copper film due to rapid copper growth, differences in growth speed of the copper film over the surface of the wafer, formation of the copper seed film indispensable for the electrolytic plating and the like. In particular, although the electrolytic plating itself is a wet process, the preceding processes are vacuum processes, which gives rise to a disadvantage in that the number of overall plating processes is increased.
Accordingly, the present invention has been created in order to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming copper interconnections of a semiconductor component using an electroless plating system, in which a metal seed for growing copper interconnections is subjected to a selective pretreating process, so as to grow copper only in corresponding interconnection regions.
That is to say, the present invention intends to grow a copper film of good quality through a surface cleaning process for a metal diffusion barrier layer and to selectively deposit copper only in a given pattern of a wafer through metal seed (gold, silver, nickel, tin, iron, palladium, etc.) pretreating and posttreating processes. In a metal seed treating process using a pretreating solution containing palladium among various kinds of metal seeds, the present invention also intends to realize selective copper deposition by providing different chemical structures of palladium particles to be adsorbed and deposited on the surface depending upon composition of the solution and a process temperature to vary deposition position and size of the palladium particles according to the surface structure of the wafer and, after this palladium treating process, selectively depositing the palladium particles through wafer cleaning.
To accomplish this object, there is provided a method for forming copper interconnections of a semiconductor component using an electroless plating system in accordance with the present invention, the method comprising: a first step of cleaning a wafer in order to remove contamination sources and allow uniform copper deposition; a second step of pretreating the wafer with a metal seed solution so as to cause copper depositing regions to tend toward spontaneous catalytic activation and simultaneously varying a process temperature to grow metal seed particles from the metal seed pretreating solution, the metal seed particles having different bonding forces and sizes on a wafer surface and in interconnection forming regions; a third step of cleaning the wafer to remove the metal seed from the wafer surface; and a fourth step of plating a product obtained from the third step with an electroless plating bath to grow copper in the metal seed formed regions.
In the above-mentioned method according to the present invention, the first step comprises the sub-steps of removing organics and metallic contaminants formed on the wafer surface by cleaning the wafer using sulfuric acid and hydrogen peroxide in a weight ratio of 1 to 10:1 for a time of 1 to 10 minutes; and removing oxides formed on the wafer surface by cleaning the wafer using hydrofluoric acid and water in a weight ratio of 1 to 10:100 for a time of 1 to 2 minutes.
Also, the metal seed used as the pretreating solution for selective copper deposition of the second step is any one selected from the group consisting of palladium (Pd), gold (Au), silver (Ag), tin (Sn), nickel (Ni), iron (Fe), copper (Cu) and platinum (Pt), and the metal seed pretreating solution using palladium is composed of a mixture of 0.01 to 0.1 g/l of palladium chloride (PdCl2), 3 to 20 ml of ammonia water (NH4OH), 1 to 20 ml of hydrochloric acid (HCl) and 1 to 10 ml of hydrofluoric acid (HF).
In this case, it is preferable that nitric acid (HNO3), as a surface oxidant, is further added to and polyethyleneglycol (PEG) and Triton, as surfactants for stabilization of the solution, is further added to the metal seed pretreating solution.
In addition, the second step of pretreating the wafer with the metal seed is performed at a process temperature of 50 to 80, thereby causing only Pd metal particles of Pd(NH3)2Cl2 within the solution to be grown on the surface.
In accordance with the pretreating process temperature of the second step, nano size fine particles of several tens of nanometers are deposited at a normal temperature and the size of the nano size particles increases up to a size of a several hundreds of nanometers at the process temperature of 50 to 80xc2x0 C.
On the other hand, a procedure for preparing the electroless plating bath prior to the copper electroless plating of the fourth step comprises the steps of a) adding copper sulfate pentahydrate and EDTA to a water solvent and then stirring the solvent to produce a solution; b) adjusting solution pH to an alkaline state by TMAH prior to putting HCHO into the solution in order to prevent a side reaction by which HCHO is rapidly converted into methanol in an acidic state; c) adding HCHO to a product obtained from step b); d) putting other additives into the solution; and e) adjusting solution pH to a value of 12 to 13 by TMAH and then stirring the solution.
Preferably, the copper electroless plating is conducted at a temperature of 50 to 80xc2x0 C.
Following the electroless plating process of the fourth step, it is preferable to further performing a planarization (CMP) process for posttreating processes.